Normally conducting dual thyristor

ABSTRACT

The present invention relates to a component forming a normally on dual thyristor, which can be turned off by a voltage pulse on the control electrode, including a thyristor, a first depletion MOS transistor, the gate of which is connected to the source, connected between the anode gate and the cathode of the thyristor, and a second enhancement MOS transistor, the gate of which is connected to a control terminal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a dual thyristor, that is, to acomponent, the features of which can be induced from those of aconventional thyristor by applying the duality principle to the currentand voltage behaviors and to the control modes.

2. Discussion of the Related Art

FIG. 1A shows a conventional thyristor Th including an anode A, acathode K, and cathode and anode gates GK and GA.

The characteristic curve of a thyristor is illustrated in FIG. 1B. Thiscomponent exhibits the following features:

it is normally off,

it is a one-way component for the current, that is, it is likely to letthrough a positive current I_(A) but blocks a negative current,

it is bidirectional for the voltage, that is, it is likely to withstandpositive or negative voltages in the off state,

it can be triggered by a current pulse applied to its gate when thevoltage thereacross is positive; this is illustrated in FIG. 1B by curve10, that is, when a gate current is applied thereto, it turns on bybreak over, and its characteristic becomes that indicated by curve 11,

it is self-triggering when the voltage thereacross exceeds a value VBOin the absence of a gate current,

it spontaneously turns off when the current flowing therethrough becomeslow (lower than a hold current value I_(H)).

The symbol of a dual thyristor is illustrated in FIG. 2A. This dualthyristor has current-voltage characteristics which are dual withrespect to those of a conventional thyristor, as is shown in FIG. 2B:

it is normally on,

it is bidirectional for the current, that is, a positive current as wellas a negative current can flow therethrough (the flowing of a negativecurrent is ensured by diode D illustrated in FIG. 2A),

it is a one-way component for the voltage, that is, it is likely towithstand positive voltages only, in the off state, due to the presenceof diode D,

it can be turned off by a voltage pulse applied to the gate, that is,if, while the operating point is on curve 20, a control voltage isapplied, the operating characteristic will become that designated withreference 21,

it has a self turn-off characteristic, that is, if the current flowingtherethrough exceeds a value I_(BO), it turns off by itself,

it spontaneously triggers at voltage zero crossing, that is, it turns onif, while in the off state, the voltage thereacross drops below athreshold voltage V_(H).

In other words, while a thyristor forms a normally off one-way componentfor the current, which can be triggered by a control current or beself-triggering beyond a given voltage threshold, a dual thyristor formsa normally on switch which can be turned off by a control voltage or beself-locking beyond a given voltage threshold.

In prior art, the implementation of a system having the function of adual thyristor has been performed by associating a specific controlcircuit with a switching component. This solution has two disadvantages.The first one is that it is always difficult to monolithically associatecontrol circuits with a power component. The second one is that it isnecessary to provide for the control circuit a bulky auxiliary powersupply, which is costly and possibly sensitive to surroundingdisturbances. A simplified dual thyristor not controllable by pulses isdescribed in EPE'95: 6TH European Conference on Power Electronics andApplication, Seville, Sep. 19-21, 1995, vol. 1, Sep. 19, 1995, P. 1.637to 1.642, X P OOO537596, J-L Sanchez et al.

SUMMARY OF THE INVENTION

Thus, an object of the present invention is to provide a simple assemblyof components having the function of a dual thyristor.

Another object of the present invention is to provide such an assemblyin the form of a monolithic component.

Another object of the present invention is to provide such a monolithiccomponent which can be manufactured by usual technologies.

To achieve these objects as well as others, the present inventionprovides a component forming a dual thyristor, which is normally on andwhich can be turned off by a voltage pulse on the control electrode,including a thyristor, a resistive means formed of a first depletion MOStransistor, the gate of which is connected to the source, the substrateof this transistor being connected to the cathode gate terminal,connected between the anode gate and the thyristor cathode, and acontrolled conduction switching means formed of a second enhancement MOStransistor, the gate of which is connected to a control terminal and thesubstrate of which is connected to the cathode gate terminal, connectedbetween the cathode gate and the thyristor cathode.

According to an embodiment of the present invention, the component ispulse-controlled and further includes means for maintaining theconduction between the cathode gate and the cathode as soon as thisconduction has been triggered by the switching means.

According to an embodiment of the present invention, the maintainingmeans include a third enhancement MOS transistor, the substrate of whichis connected to the cathode gate terminal, in parallel on the secondenhancement MOS transistor; a zener diode connected between the cathodeof the thyristor and a node connected to the gate of the thirdtransistor; and a fourth depletion MOS transistor connected between saidnode and the anode gate of the thyristor, the gate of the fourthtransistor being connected to the cathode and its substrate beingconnected to said node.

According to an embodiment of the present invention, a low leakagecurrent component is made by providing, in series with the firstdepletion MOS transistor, a second switching means, normally on andturned off after a control order has been applied to the secondtransistor.

According to an embodiment of the present invention, the secondswitching means is a floating substrate P-channel depletion MOStransistor, the gate of which is connected to said node.

According to an embodiment of the present invention, the thyristor isimplemented in vertical form in a silicon substrate of a firstconductivity type; the first depletion MOS transistor is implementedbetween the cathode region of the thyristor and the substrate; each ofthe second and third MOS enhancement transistors is formed between tworegions of the first conductivity type formed in a first cathode gatewell of the thyristor, one of these two regions corresponding to thecathode region of the thyristor; the fourth depletion MOS transistor isformed between a region of the first conductivity type, itself formed ina second well of the second conductivity type separated from the gatewell of the thyristor, and the substrate; and the zener diode is formedin the second well.

According to an embodiment of the present invention, the component isformed from a substrate of the first conductivity type, the rear surfaceof which is coated with a layer of the second conductivity type coatedwith a first metallization and includes on its front surface side afirst well of the second conductivity type containing first, second,third and fourth regions of the first conductivity type, the first andsecond regions being separated by a portion of the first well coatedwith a first insulated gate metallization, the third and fourth regionsbeing separated by a portion of the first well coated with a secondinsulated gate metallization, a portion at least of the first wellseparating the first and/or the fourth region from the substrateincluding at its upper surface a first preformed channel region coatedwith a third insulated gate metallization, a second metallizationcoating the first region, a third metallization coating the second andthird regions and a portion of the upper surface of the first well, afourth metallization coating the fourth region; and a second well of thesecond conductivity type including fifth and sixth regions of the firstconductivity type, the fifth region being separated from the substrateby a second preformed channel region coated with a fourth insulated gatemetallization, the sixth region forming with the second well a zenerjunction, a fifth metallization coating the fifth and sixth regions andconnecting them to the second well, a sixth metallization being incontact with a portion of the second well, a sixth metallization beingin contact with a portion of the second well neighboring the sixthregion. The second insulated gate metallization is meant to be connectedto a control terminal; the second, fourth, and sixth metallizations aswell as the third and fourth insulated gate metallizations are meant tobe connected to a cathode terminal, the fifth metallization beingconnected to the first insulated gate metallization.

According to an embodiment of the present invention, the thyristor isimplemented in vertical form in a silicon substrate of a firstconductivity type; the first depletion MOS transistor is formed in athird well separated from the first cathode gate well of the thyristor,between a region formed in this third well and the substrate; each ofthe second and third enhancement MOS transistors is formed between aregion of the first conductivity type, formed in the cathode gate wellof the thyristor, and the cathode region of the thyristor; the fourthdepletion MOS transistor is formed between a region of the firstconductivity type, itself formed in a second well of the secondconductivity type separated from the gate well of the thyristor, and thesubstrate; the zener diode is formed in the second well; and the fifthP-channel depletion MOS transistor is formed between the second well andan additional region of the second conductivity type.

According to an embodiment of the present invention, the component isformed from a substrate of the first conductivity type, the rear surfaceof which is coated with a layer of the second conductivity type coatedwith a first metallization and includes, on its front surface side, afirst well of the second conductivity type containing first, second, andthird regions of the first conductivity type, the first and secondregions being separated by a portion of the first well coated with afirst insulated gate metallization, the first and third regions beingseparated by a portion of the first well coated with a second insulatedgate metallization, the first region being coated with a secondmetallization, the second region being coated with a third metallizationextending over a portion of the first well, the third region beingcoated with a fourth metallization extending over a portion of the firstwell; a second well of the second conductivity type including fourth andfifth regions of the first conductivity type, the fourth region beingseparated from the substrate by a first preformed channel region coatedwith a third insulated gate metallization, the fifth region forming withthe second well a zener junction, a fifth metallization coating thefourth and fifth regions and connecting them to the second well, a sixthmetallization being in contact with a portion of the second wellneighboring the fifth region; and a third well of the secondconductivity type containing a sixth region of the first conductivitytype, a portion at least of the well separating the sixth region fromthe substrate including at its upper surface a second preformed channelregion coated with a fourth insulated gate metallization, the third wellbeing separated from a region of the second conductivity type by alightly-doped region of the second conductivity type coated with a fifthinsulated gate metallization, the sixth region and a portion of theupper surface of the third well being coated with a seventhmetallization, the upper surface of the lightly-doped region of thesecond conductivity type being coated with an eighth metallization. Thefirst insulated gate metallization is meant to be connected to a controlterminal; the second, sixth, and eighth metallizations as well as thethird and fourth insulated gate metallizations are meant to be connectedto a cathode terminal, the fifth metallization being connected to thesecond and fifth insulated gate metallizations.

According to an embodiment of the present invention, each of the wellsincludes more heavily-doped areas at least at the locations where ametallization is in contact with a portion of their upper surface.

The foregoing objects, features and advantages of the present inventionwill be discussed in detail in the following non-limiting description ofspecific embodiments in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWING

FIGS. 1A and 1B show a thyristor and its current-voltage characteristic;

FIGS. 2A and 2B show a dual thyristor and its current-voltagecharacteristic;

FIGS. 3A and 3B show a first example of a circuit forming a dualthyristor according to the present invention;

FIG. 4 shows a second example of a circuit forming a dual thyristoraccording to the present invention;

FIG. 5 shows a third example of a circuit forming a dual thyristoraccording to the present invention;

FIG. 6 shows a simplified cross-sectional view of a semiconductorcomponent implementing the functions of the circuit of FIG. 4; and

FIG. 7 shows a simplified cross-sectional view of a semiconductorcomponent implementing the functions of the circuit of FIG. 5.

DETAILED DESCRIPTION

FIG. 3A shows a first embodiment of a dual thyristor according to thepresent invention. This dual thyristor is built from a thyristor Thhaving an anode terminal A, a cathode terminal K, a cathode gateterminal GK and an anode gate terminal GA. Terminal GA is connected toterminal K via a depletion N-channel MOS transistor M_(D) 1. The gate oftransistor M_(D) 1 is also connected to terminal K. Terminal GK isconnected to terminal K via an enhancement N-channel MOS transistorM_(E) 2. The drain of transistor M_(E) 2, connected to terminal GK, isalso connected to the substrate of transistor M_(E) 2. The gate oftransistor M_(E) 2 is connected to a control terminal G. The substratesof transistors M_(D) 1 and M_(E) 2 are connected to terminal GK.

The operation of this circuit is the following. As soon as anode-cathodevoltage V_(AK) increases positively, an anode gate current flows fromterminal A to terminal K through anode gate GA and transistor M_(D) 1which is normally on. Accordingly, thyristor Th turns on and acts as aclosed switch.

To turn off thyristor Th, a voltage which is positive with respect tothe cathode has to be applied on gate terminal G of transistor M_(E) 2.Transistor M_(E) 2 then short-circuits the cathode and the cathode gateof the thyristor and turns it off.

A normally on component controlled to be turned off has thus beenobtained. However, if the control voltage on terminal G is interrupted,the component turns back on.

Further, to form a bidirectional dual thyristor for the current, a diodeD is connected by its anode to terminal K and by its cathode to terminalA. This diode has not been shown for simplicity, neither in thisdrawing, nor in the following drawings.

FIG. 3B reproduces the circuit of FIG. 3A. Thyristor Th has beenconventionally shown by its two equivalent transistors T1 and T2. Thisequivalent diagram could be used each time a thyristor has been shown.

FIG. 4 shows a modification of the circuit of FIG. 3A enabling tocontrol the component with pulses, that is, the component is set to theoff state by a control pulse, then remains off while the voltagethereacross remains positive, even if no control signal is maintained.

Elements Th, M_(D) 1, and M_(E) 2 described in relation with FIG. 3Areappear in FIG. 4. Further, an enhancement MOS transistor M_(E) 3 isconnected in parallel, by its main terminals, on transistor M_(E) 2. Thegate of transistor M_(E) 3 is connected to a node C. Node C is connectedto the cathode of a zener diode Z, the anode of which is connected toterminal K. Node C is also connected to terminal GA via a depletionN-channel MOS transistor M_(D) 4, the gate of which is connected toterminal K. Each of transistors M_(E) 3 and M_(D) 4 has its sourceconnected to its substrate.

The turning-on of thyristor Th is ensured as previously by depletion MOStransistor M_(D) 1. Once a turn-off order is applied on gate terminal Gof transistor M_(E) 2, the voltage on terminal A and thus on terminal GAincreases with respect to the voltage on terminal K. The voltage onterminal GA reappears via transistor M_(D) 4 on node C, that is, on thegate of transistor M_(E) 3. Transistor M_(E) 3 turns on and maintainsthe short-circuit state between the cathode and the cathode gate ofthyristor Th, even if the control on gate G is interrupted. Zener diodeZ is used to limit the gate voltage of transistor M_(E) 3.

Thus, the dual thyristor of FIG. 4 can effectively be controlled to beturned off by a pulse on terminal G and remains off as long as thevoltage on terminal C remains higher than the threshold voltage oftransistor M_(E) 3, that is, substantially as long as voltage V_(AK) ishigher than the threshold voltage of transistor M_(E) 3.

The circuit of FIG. 4 has a disadvantage in that, in the off state,there remains a leakage current through depletion transistor M_(D) 1. Tolimit this leakage current, the resistance in the on state of transistorM_(D) 1 should be increased, which would have disadvantages as concernsthe sensitivity of the initial turning-on of the dual thyristor.

To overcome this disadvantage, according to an alternative of thepresent invention, it is provided to arrange in series with transistorM_(D) 1 a switch which is opened when the device switches to the offstate. FIG. 5 shows an example of implementation of such a structuresuppressing the off-state leakage current.

The circuit of FIG. 5 is identical to that of FIG. 4 with the additionof a floating substrate depletion P-channel MOS transistor M_(D) 5 inseries with transistor M_(D) 1 between terminals GA and K. The gate oftransistor M_(D) 5 is connected to node C.

Thus, when the anode-cathode voltage becomes positive from a zero value,depletion MOS transistors M_(D) 1 and M_(D) 5 are both on and triggerthyristor Th. When the device is off, as has been described in relationwith FIG. 4, the increase of the potential on node C turns offtransistor M_(D) 5. A substantially total canceling of the leakagecurrent is thus obtained.

In the foregoing description, the self turn-off function when thecurrent through the dual thyristor exceeds a determined threshold hasnot been described. Indeed, this feature is seldom useful in practicalapplications. It however exists in the embodiments of FIGS. 4 and 5 andintervenes when the current through thyristor Th induces therein avoltage drop higher than the sum of the threshold voltage of transistorM_(E) 3 and of the saturation voltage of transistor M_(D) 4.

FIGS. 6 and 7 very schematically show simplified cross-sectional viewsof monolithic semiconductive structures respectively implementing thecircuits of FIGS. 4 and 5.

As is usual in the field of the representation of semiconductorcomponents, the several layers and regions of these structures are notdrawn to scale but their dimensions have been arbitrarily modified toimprove the readability and facilitate the drawings.

The shown structures are formed from a lightly-doped N-type substrate 1,the rear surface of which is coated with a P⁺-type layer 2 uniformlycoated with an anode metallization M1. It should be noted that, if it isdesired to provide the structure with an antiparallel diode, it could beprovided to partially interrupt P⁺-type region 2 and to diffuse,instead, an N⁺-type region in front of a P⁺-type region formed on theupper surface side, as is indicated in the left-hand portion of FIGS. 6and 7.

In FIG. 6, on the upper surface side, four types of regions are to befound:

heavily-doped P-type regions (P⁺),

more lightly-doped P-type regions (P),

heavily-doped N-type regions (N⁺), and

more lightly-doped N-type regions corresponding to the preformedchannels of depletion N-channel MOS transistors.

FIG. 7 further shows a lightly-doped P-type region 96 meant to form thepreformed channel of the floating substrate depletion P-channel MOStransistor M_(D) 5.

In FIG. 6, two P-type wells 61 and 62 are formed on the upper surfaceside of the substrate.

In well 61, an N⁺-type region 63 forms the cathode region of thyristorTh. A portion 64 of well 61, intermediary between region 63 and an upperportion of substrate 1, is replaced with a lightly-doped N-type regionforming a preformed channel for transistor M_(D) 1. This region 64 iscoated with an insulated gate metallization G1. Metallization G1 may beformed of an extension of a metallization M2 coating region 63 andforming the cathode metallization of the thyristor.

In well 61, between region 63 and another N⁺-type region 65 is formed anenhancement N-channel MOS transistor, the channel region of which iscoated with an insulated gate metallization G3. This transistorcorresponds to transistor M_(E) 3 of FIG. 4.

In well 61, enhancement MOS transistor M_(E) 2 is also formed betweenN⁺-type regions 66 and 67. The gate of this transistor is designatedwith reference G2. A metallization M3 is in contact with the uppersurfaces of regions 65 and 66 and with a P⁺ overdoped region 68 of well61. A metallization M4 covers region 67. Metallization M4 is connectedto terminal K and, as an example of an alternative of the presentinvention, an extension of this metallization M4 forming a gate G′1 ofanother portion of depletion transistor M_(D) 1 above a lightly-dopedN-type region 69 extending between region 67 and an upper surfaceportion of substrate 1 has been shown.

In well 62 are formed N⁺-type regions 71 and 72. A preformed channelregion 73 extends at the upper surface of the component between region71 and an upper portion of substrate 1. This channel is coated with aninsulated gate G4. A metallization M5 covers the upper portion of region71, an apparent surface of an overdoped region 75 of well 62, and theupper surface of region 72. A metallization M6 is in contact with anapparent overdoped portion 76 of well 62. Metallization M5 is connectedto metallization G3 which corresponds to terminal C. Metallization M6 isconnected to cathode gate K.

To properly understand how the structure of FIG. 6 corresponds to thecircuit of FIG. 4, it should be noted that well 61 corresponds tocathode gate GK of thyristor Th and that substrate 1 corresponds to itsanode gate GA. Thus:

thyristor Th includes, between metallizations M1 and M2, regions2-1-61-63;

transistor M_(D) 1 has a source 63 (67) connected to terminal K bymetallization M2 (M4), a gate G1 (G′1) connected to cathode K, and adrain which corresponds to substrate 1; the substrate of this transistorM_(D) 1 corresponds to well 61, that is, to terminal GK;

transistor M_(E) 2 has a drain 66 which is connected by metallization M3to region 61, which corresponds to the substrate of transistor M_(E) 2and to terminal GK; its gate G2 is connected to a control terminal G;and its source 67 is connected by metallization M4 to terminal K;

transistor M_(E) 3 has, as a source, region 63 confounded with thecathode region of the thyristor, and as a drain, region 65 connected bymetallization M3 to its substrate which also is area 68 corresponding toa portion of cathode gate layer 61;

transistor M_(D) 4 has, as a source, region 71 connected bymetallization M5 to the substrate of this transistor and to node C andhas, as a drain, substrate 1;

zener diode Z corresponds to the junction between well 62 and region 72.Its cathode corresponds to region 72 and is connected by metallizationM5 to node C. Its anode corresponds to an overdoped region 76 of well 62and is connected by metallization M6 to terminal K.

Further, as has been previously indicated, an antiparallel diode isformed between a P⁺ region 100 coated with a metallization M100 on theupper surface side and an N⁺ region 101 coated with metallization M1 onthe lower surface side.

It should be noted that this structure is likely to have a great numberof alternative modes of implementation, provided that the functionsdescribed hereabove of a thyristor, of four MOS transistors and of azener diode are implemented.

Moreover, in the above description of an example of monolithicintegration of the circuit of FIG. 5, alternative implementations havebeen provided for several elements. Further, the metallizationsschematically shown as connected by wires to terminal K or to node C canbe formed of one and the same metallization if the topologicalconsiderations enable it.

FIG. 7 shows an embodiment of the circuit of FIG. 5.

The left-hand portion of FIG. 7 shows wells and regions 62, 71, 72, 73,75, 76 identical to what is shown in FIG. 6 and coated withmetallizations M6, M5, and G4. This assembly forms, as in FIG. 6, animplementation of transistor M_(D) 4 and of diode Z.

The central portion of FIG. 7 shows a P-type well 81, the periphery ofwhich is formed of a more heavily-doped P⁺-type region 82. In this well,a main N⁺-type region 83 forms the thyristor cathode and is coated witha metallization M2. Two wells 84 and 85 form the drains of transistorsM_(E) 2 and M_(E) 3 and are separated from region 83 by portions of well81 coated with insulated gate metallizations G2 and G3. Metallization G2is connected to a control gate G. Metallization G3 is connected to nodeC. Region 84 and a portion of overdoped region 82 of the well are coatedwith a metallization M7 corresponding to the source-substrate connectionof transistor M_(E) 2 and to a connection between this source and well81 which corresponds to the cathode gate of the thyristor. Similarly,region 85 is connected to a portion of region 82 by a metallization M8.

The right-hand portion of FIG. 7 shows a P⁺-type well 91 in which isformed an N⁺-type region 92. A lightly-doped N-channel preformed channelregion 93 extends between region 92 and an upper portion of substrate 1.This preformed channel region is coated with an insulated gate G1connected to cathode K. A metallization M9 connects the apparentsurfaces of regions 91 and 92. Further, in the immediate vicinity ofheavily-doped P-type region 91 is formed a heavily-doped P-type region95. Regions 91 and 95 are separated by a lightly-doped P-type preformedchannel region 96 and region 95 is coated with a metallization M10connected to cathode K.

This structure thus comprises:

a thyristor Th formed of regions 2-1-81-83 between metallizations M1 andM2 (terminals A and K),

a MOS transistor M_(D) 1, the source of which corresponds to region 92,the drain of which corresponds to substrate 1, and the gate of whichcorresponds to metallization G1,

a MOS transistor M_(E) 2, the source of which corresponds to region 83,the drain of which corresponds to region 84, and the gate of whichcorresponds to metallization G2,

a MOS transistor M_(E) 3, the source of which corresponds to region 83,the drain of which corresponds to region 85, the gate of whichcorresponds to metallization G3, and the substrate of which correspondsto region 81,

a MOS transistor M_(E) 4 identical to that of FIG. 6,

a zener diode Z identical to that of FIG. 6,

a floating substrate depletion P-channel MOS transistor M_(D) 5, thesource of which corresponds to region 91, the drain of which correspondsto region 95, the gate of which corresponds to metallization G5, and thesubstrate of which corresponds to substrate 1.

Of course, the present invention is likely to have various alterations,modifications and improvements which will readily occur to those skilledin the art. The improvements usually brought to thyristors (emittershort-circuits) may be used. Channel stop regions and regions ofinsulation between components may also be provided.

What is claimed is:
 1. A component forming a dual thyristor, which isnormally on and which can be turned off by a voltage pulse on a controlelectrode, including: a thyristor (Th) having a cathode (K), an anode, acathode gate (GK) and an anode gate (GA), resistive means formed of afirst depletion MOS transistor (M_(D) 1) having a drain, a source, agate and a substrate, the gate being connected to the source, thesubstrate being connected to the cathode gate terminal, said firsttransistor being connected between the anode gate (GA) and the cathode(K), and a controlled switching means formed of a second enhancement MOStransistor (M_(E) 2) having a drain, a source, a gate and a substrate,the gate being connected to a control terminal (G) and the substratebeing connected to the cathode gate (GK) terminal, said secondtransistor being connected between the cathode gate (GK) and the cathode(K), and, maintaining means for maintaining conduction between thecathode gate and cathode in response to said switching means comprising:a third enhancement MOS transistor (M_(E) 3) having a gate, a source, adrain and a substrate, the substrate of which is connected to thecathode gate terminal (GK), in parallel with the second transistor(M_(E) 2); a zener diode (Z) connected between the cathode of thethyristor and a node (C) connected to the gate of the third transistor(M_(E) 3); and a fourth depletion MOS transistor (M_(D) 4) having agate, a source, a drain and a substrate and connected between said node(C) and the anode gate of the thyristor, the gate of the fourthtransistor being connected to the cathode (K) and its substrate beingconnected to said node (C).
 2. The component of claim 1, including, inseries with the first depletion MOS transistor (M_(D) 1), a secondswitching means, normally on and turned off after a control order hasbeen applied to the second transistor (M_(E) 2).
 3. The component ofclaim 2, wherein the second switching means is a floating substrateP-channel depletion MOS transistor (M_(D) 5), the gate of which isconnected to said node (C).
 4. The component of claim 1, wherein: thethyristor (Th) is implemented in vertical form in a silicon substrate(1) of a first conductivity type; the first depletion MOS transistor(M_(D) 1) is implemented between a cathode region (63) of the thyristorand the substrate; each of the second and third enhancement MOStransistors (M_(E) 2, M_(E) 3) is formed between two regions (63, 65;66, 67) of the first conductivity type formed in a first cathode gatewell (61) of the thyristor, one of these two regions (63; 67)corresponding to the cathode region of the thyristor; the fourthdepletion MOS transistor (M_(D) 4) is formed between a region of thefirst conductivity type (71), itself formed in a second well (62) of asecond conductivity type (67) separated from the gate well of thethyristor, and the substrate; and the zener diode (Z) is formed in thesecond well (62).
 5. The monolithic component of claim 4, formed from asubstrate (1) of the first conductivity type, the rear surface of whichis coated with a layer (2) of the second conductivity type coated with afirst metallization (M1), and including, on its front surface side: afirst well (61) of the second conductivity type containing first (63),second (65), third (66), and fourth (67) regions of the firstconductivity type, the first and second regions being separated by aportion of the first well coated with a first insulated gatemetallization (G3), the third and fourth regions being separated by aportion of the first well coated with a second insulated gatemetallization (G2), a portion at least of the first well separating thefirst (63) and/or the fourth (67) region from the substrate (1)including at its upper surface a first preformed channel region (64; 69)coated with a third insulated gate metallization (G1; G′1), a secondmetallization (M2) coating the first region (63), a third metallization(M3) coating the second (65) and third (66) regions and a portion of theupper surface of the first well, a fourth metallization (M4) coating thefourth region; and a second well (62) of the second conductivity typeincluding fifth (71) and sixth (72) regions of the first conductivitytype, the fifth region (71) being separated from the substrate by asecond preformed channel region (73) coated with a fourth insulated gatemetallization (G4), the sixth region (72) forming with the second well azener junction, a fifth metallization (M5) coating the fifth and sixthregions and connecting them to the second well, a sixth metallizationbeing in contact with a portion of the second well (62), a sixthmetallization (M6) being in contact with a portion of the second well(62) neighboring the sixth region (72); the second insulated gatemetallization (G2) being meant to be connected to a control terminal(G), the second (M2), fourth (M4), and sixth (M6) metallizations as wellas the third (G1) and fourth (G4) insulated gate metallizations beingmeant to be connected to a cathode terminal (K), the fifth metallization(M5) being connected to the first insulated gate metallization (G3)(node C).
 6. The monolithic component of claim 3, wherein: the thyristor(Th) is implemented in vertical form in a silicon substrate (1) of afirst conductivity type; the first depletion MOS transistor (M_(D) 1) isformed in a third well (91) separated from the first cathode gate well(81) of the thyristor, between a region (92) formed in this third welland the substrate; each of the second and third enhancement MOStransistors (M_(E) 2, M_(E) 3) is formed between a region (84; 85) ofthe first conductivity type, formed in the cathode gate well (81) of thethyristor, and the cathode region (83) of the thyristor; the fourthdepletion MOS transistor (M_(D) 4) is formed between a region of thefirst conductivity type (71), itself formed in a second well (62) of thesecond conductivity type separated from the gate well of the thyristor,and the substrate; the zener diode (Z) is formed in the second well(62); and the fifth P-channel depletion MOS transistor (M_(D) 5) isformed between the second well (91) and an additional region (95) of thesecond conductivity type.
 7. The monolithic component of claim 6, formedfrom a substrate (1) of the first conductivity type, the rear surface ofwhich is coated with a layer (2) of the second conductivity type coatedwith a first metallization (M1) and including, on its front surfaceside: a first well (81) of the second conductivity type containing first(83), second (84), and third regions (85) of the first conductivitytype, the first and second regions being separated by a portion of thefirst well coated with a first insulated gate metallization (G2), thefirst and third regions being separated by a portion of the first wellcoated with a second insulated gate metallization (G3), the first region(83) being coated with a second metallization (M2), the second region(84) being coated with a third metallization (M7) extending over aportion of the first well, the third region (85) being coated with afourth metallization (M8) extending over a portion of the first well; asecond well (62) of the second conductivity type including fourth (71)and fifth (72) regions of the first conductivity type, the fourth region(71) being separated from the substrate by a first preformed channelregion (73) coated with a third insulated gate metallization (G4), thefifth region (72) forming with the second well a zener junction, a fifthmetallization (M5) coating the fourth (71) and fifth (72) regions andconnecting them to the second well (62), a sixth metallization (M6)being in contact with a portion of the second well (62) neighboring thefifth region (72); and a third well (91) of the second conductivity typecontaining a sixth region (92) of the first conductivity type, a portionat least of the well separating the sixth region (92) from the substrate(1) including at its upper surface a second preformed channel region(93) coated with a fourth insulated gate metallization (G1), the thirdwell (91) being separated from a region (95) of the second conductivitytype by a lightly-doped region (96) of the second conductivity typecoated with a fifth insulated gate metallization (G5), the sixth regionand a portion of the upper surface of the third well being coated with aseventh metallization (M9), the upper surface of the lightly-dopedregion (96) of the second conductivity type being coated with an eighthmetallization (M10); the first insulated gate metallization (G2) beingmeant to be connected to a control terminal (G), the second (M2), sixth(M6), and eighth (M10) metallizations as well as the third (G4) andfourth (G1) insulated gate metallizations being meant to be connected toa cathode terminal (K), the fifth metallization (M5) being connected tothe second (G3) and fifth (G5) insulated gate metallizations (node C).8. The monolithic component of claim 5, wherein each of the wellsincludes more heavily-doped areas at least at the locations where ametallization is in contact with a portion of their upper surface.